SI5341B-B-GM Overview
As a clock IC, it uses the Tray package. 64-VFQFN Exposed Pad contains this Clock PLL. When reflowed, this frequency generator can withstand a maximum temperature of NOT SPECIFIED. As a result, frequency synthesizers can be found to contain 64 terminations. For this clock generator ic, a voltage of 1.8V is required. This Clock PLL will be fed by LVCMOS, LVDS, LVPECL, Crystal as its input. There are 1 circuits implemented in order to achieve full performance from this electronic part. The Surface Mount allows this electrical component to be easily installed on the panel. This RF synthesizer has CLOCK GENERATOR, PROCESSOR SPECIFIC uPs, uCs, and peripheral ICs. There are 1.71V~3.47V different supply voltages that can be provided for this RF synthesizer. Based on test statistics, ambient temperature should be set at -40°C~85°C. I would like to present to you a frequency synthesizer that is compatible with CML, HCSL, LVCMOS, LVDS, LVPECL logic levels. In order to provide better clock signal output, this frequency synthesizer is equipped with ALSO REQUIRES 3.3V SUPPLY. At a frequency of 350MHz, the system can achieve high efficiency.
SI5341B-B-GM Features
Available in the 64-VFQFN Exposed Pad
Supply voltage of 1.8V

SI5341B-B-GM Applications
There are a lot of Silicon Labs
SI5341B-B-GM Clock Generators applications.

Sampling clocks for ADC and DAC
1 Gigabit Ethernet
10 Gigabit Ethernet
FPGA and processor clocks
Line cards used in telephone exchange
Fiber Channel
PCI express cards
Infotainment systems
Medical equipment
Multi-function printers

Factory Lead Time	4 Weeks
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	64-VFQFN Exposed Pad
Operating Temperature	-40°C~85°C
Packaging	Tray
Published	2014
JESD-609 Code	e4
Part Status	Not For New Designs
Moisture Sensitivity Level (MSL)	2 (1 Year)
Number of Terminations	64
ECCN Code	EAR99
Terminal Finish	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
Additional Feature	ALSO REQUIRES 3.3V SUPPLY
Voltage - Supply	1.71V~3.47V
Terminal Position	QUAD
Terminal Form	NO LEAD
Peak Reflow Temperature (Cel)	NOT SPECIFIED
Supply Voltage	1.8V
Terminal Pitch	0.5mm
Frequency	350MHz
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED
Output	CML, HCSL, LVCMOS, LVDS, LVPECL
JESD-30 Code	S-XQCC-N64
Number of Circuits	1
uPs/uCs/Peripheral ICs Type	CLOCK GENERATOR, PROCESSOR SPECIFIC
Input	LVCMOS, LVDS, LVPECL, Crystal
Ratio - Input:Output	4:10
Primary Clock/Crystal Frequency-Nom	54MHz
PLL	Yes
Differential - Input:Output	Yes/Yes
Divider/Multiplier	Yes/No
Length	9mm
Height Seated (Max)	0.9mm
Width	9mm
RoHS Status	RoHS Compliant