SI5341C-B-GM Overview
In order to package it as a clock IC, the Tray package is used. A Clock PLL is included with the 64-VFQFN Exposed Pad package. Frequency generator can maintain a maximum temperature of NOT SPECIFIED under reflowing conditions. As a result of this, we can find 64 terminations. Clock generator ics require a voltage of 1.8V. As the Clock PLL's input, LVCMOS, LVDS, LVPECL, Crystal is designed to be used in order to generate the clock signal. It is possible to access the full performance of the electrical part by implementing 1 circuits. It provides a maximum frequency of 712.5MHz. Surface Mount-slots make it easy to mount this electronic component on panels. The number of uPs/uCs/PEripheral ICs contained in this clock generator is CLOCK GENERATOR, PROCESSOR SPECIFIC. Clock generator ic works with 1.71V~3.47V. By calculating the test statistics, -40°C~85°C is the appropriate ambient temperature. CML, HCSL, LVCMOS, LVDS, LVPECL logic levels are supported by this RF synthesizer. This frequency synthesizer features ALSO REQUIRES 3.3V SUPPLY to produce better clock signals.
SI5341C-B-GM Features
Available in the 64-VFQFN Exposed Pad
Supply voltage of 1.8V

SI5341C-B-GM Applications
There are a lot of Silicon Labs
SI5341C-B-GM Clock Generators applications.

10 Gigabit Ethernet
FPGA and processor clocks
Line cards used in telephone exchange
Fiber Channel
PCI express cards
Infotainment systems
Medical equipment
Multi-function printers
Media broadcast servers
Test equipment

Factory Lead Time	4 Weeks
Mount	Surface Mount
Mounting Type	Surface Mount
Package / Case	64-VFQFN Exposed Pad
Operating Temperature	-40°C~85°C
Packaging	Tray
Published	2014
Part Status	Not For New Designs
Moisture Sensitivity Level (MSL)	2 (1 Year)
Number of Terminations	64
ECCN Code	EAR99
Additional Feature	ALSO REQUIRES 3.3V SUPPLY
Voltage - Supply	1.71V~3.47V
Terminal Position	QUAD
Terminal Form	NO LEAD
Peak Reflow Temperature (Cel)	NOT SPECIFIED
Supply Voltage	1.8V
Terminal Pitch	0.5mm
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED
Output	CML, HCSL, LVCMOS, LVDS, LVPECL
JESD-30 Code	S-XQCC-N64
Number of Circuits	1
uPs/uCs/Peripheral ICs Type	CLOCK GENERATOR, PROCESSOR SPECIFIC
Frequency (Max)	712.5MHz
Input	LVCMOS, LVDS, LVPECL, Crystal
Ratio - Input:Output	4:10
Primary Clock/Crystal Frequency-Nom	54MHz
PLL	Yes
Differential - Input:Output	Yes/Yes
Divider/Multiplier	Yes/No
Length	9mm
Height Seated (Max)	0.9mm
Width	9mm
RoHS Status	RoHS Compliant