SI5325A-C-GM OverviewClock ICs are packaged using the Tray method. In the 36-VFQFN Exposed Pad package, there is an embedded clock generator. A maximum temperature of 260 can be sustained by this clock generator ic during reflowing. There are a total of 36 terminations in this file. A voltage of 1.8V should be applied to this electronic frequency generator. In this case, Clock is designed to be the input of the clock generator. To access the electronic component's full performance, 1 circuits are implemented. The frequency generator has a maximum frequency of 1.4GHz. Thanks to the Surface Mount, this electric component can easily be installed on a panel. There are 1.71V~3.63V available for use with this clock PLL. Test statistics suggest setting the ambient temperature at -40°C~85°C, which is -40°C~85°C. There are several logic levels in CML, LVCMOS, LVDS, LVPECL logic that can be used with this clock generator. It is possible to classify this electronic component as a Clock Multiplier. An IC that generates clocks specifically for microprocessors, this clock PLL is 36-bits in si36e. The related electrical components for the base part number SI5325 can be found below. A 36 pin is available on the clock PLL. Clock PLL is capable of handling a voltage of 3.3V. It is part of the DSPLL® series of electronic components. The output frequency is magnified as high as possible with 2 signal outputs. A SONET;SDH-axis phase locked loop can be used.
SI5325A-C-GM FeaturesAvailable in the 36-VFQFN Exposed Pad
Supply voltage of 1.8V
Operating supply voltage of 3.3V
SI5325A-C-GM ApplicationsThere are a lot of Silicon Labs
SI5325A-C-GM Clock Generators applications.
Wide area power system
Digital circuits
Wireless base station for LTE, LTE-advanced
Picocells, femtocells and small cells
Sampling clocks for ADC and DAC
1 Gigabit Ethernet
10 Gigabit Ethernet
FPGA and processor clocks
Line cards used in telephone exchange
Fiber Channel
| Factory Lead Time | 6 Weeks |
| Mounting Type | Surface Mount |
| Package / Case | 36-VFQFN Exposed Pad |
| Surface Mount | YES |
| Number of Pins | 36 |
| Weight | 92.589543mg |
| Operating Temperature | -40°C~85°C |
| Packaging | Tray |
| Series | DSPLL® |
| Published | 1997 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 2 (1 Year) |
| Number of Terminations | 36 |
| Type | Clock Multiplier |
| Applications | SONET;SDH |
| Voltage - Supply | 1.71V~3.63V |
| Terminal Position | QUAD |
| Peak Reflow Temperature (Cel) | 260 |
| Number of Functions | 1 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | SI5325 |
| Output | CML, LVCMOS, LVDS, LVPECL |
| Pin Count | 36 |
| Number of Outputs | 2 |
| Operating Supply Voltage | 3.3V |
| Number of Circuits | 1 |
| Frequency (Max) | 1.4GHz |
| Input | Clock |
| Ratio - Input:Output | 2:2 |
| PLL | Yes |
| Differential - Input:Output | Yes/Yes |
| Length | 6mm |
| Height Seated (Max) | 0.9mm |
| Width | 6mm |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |