SI5345A-D-GM Overview
Clock ICs are packaged using the Tray method. In the 64-VFQFN Exposed Pad package, there is an embedded clock generator. A maximum temperature of 260 can be sustained by this clock generator ic during reflowing. There are a total of 64 terminations in this file. A voltage of 1.8V should be applied to this electronic frequency generator. In this case, LVCMOS, LVDS, LVPECL, Crystal is designed to be the input of the clock generator. To access the electronic component's full performance, 1 circuits are implemented. The frequency generator has a maximum frequency of 1.028GHz. Thanks to the Surface Mount, this electric component can easily be installed on a panel. There are CLOCK GENERATOR, PROCESSOR SPECIFIC uPs/uCs/Peripheral ICs integrated into this digital clock generator. There are 1.71V~3.47V available for use with this clock PLL. Test statistics suggest setting the ambient temperature at -40°C~85°C, which is -40°C~85°C. There are several logic levels in CML, HCSL, LVCMOS, LVDS, LVPECL logic that can be used with this clock generator. With ALSO REQUIRES 3.3V SUPPLY, this clock generator produces better clock signals.
SI5345A-D-GM Features
Available in the 64-VFQFN Exposed Pad
Supply voltage of 1.8V

SI5345A-D-GM Applications
There are a lot of Silicon Labs
SI5345A-D-GM Clock Generators applications.

Wide area power system
Digital circuits
Wireless base station for LTE, LTE-advanced
Picocells, femtocells and small cells
Sampling clocks for ADC and DAC
1 Gigabit Ethernet
10 Gigabit Ethernet
FPGA and processor clocks
Line cards used in telephone exchange
Fiber Channel

Factory Lead Time	6 Weeks
Mounting Type	Surface Mount
Package / Case	64-VFQFN Exposed Pad
Surface Mount	YES
Operating Temperature	-40°C~85°C
Packaging	Tray
Published	2016
JESD-609 Code	e4
Part Status	Active
Moisture Sensitivity Level (MSL)	2 (1 Year)
Number of Terminations	64
ECCN Code	EAR99
Terminal Finish	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
Additional Feature	ALSO REQUIRES 3.3V SUPPLY
Voltage - Supply	1.71V~3.47V
Terminal Position	QUAD
Terminal Form	NO LEAD
Peak Reflow Temperature (Cel)	260
Supply Voltage	1.8V
Terminal Pitch	0.5mm
Time@Peak Reflow Temperature-Max (s)	40
Output	CML, HCSL, LVCMOS, LVDS, LVPECL
JESD-30 Code	S-XQCC-N64
Number of Circuits	1
uPs/uCs/Peripheral ICs Type	CLOCK GENERATOR, PROCESSOR SPECIFIC
Frequency (Max)	1.028GHz
Input	LVCMOS, LVDS, LVPECL, Crystal
Ratio - Input:Output	5:10
PLL	Yes
Differential - Input:Output	Yes/Yes
Divider/Multiplier	Yes/No
Length	9mm
Height Seated (Max)	0.9mm
Width	9mm
RoHS Status	Non-RoHS Compliant